SELSE Workshop

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SELSE 2 Recap

SELSE 2 Recap

Presented at SELSE 2, 2006

Presentation: presentation

Final day recap of the SELSE 2 workshop held at University of Illinois, Urbana-Champaign (UIUC). Key observations were agreed upon as the collective outcome of SELSE 2.

Soft error is a concern (we are all here)
- Multi-bit errors can not be ignored
- Latch sensitivities are approaching SRAM
- 0.001 FIT/flip flop is representative of a sensitive flip flop design in bulk technology
- 0.5 fC to upset the most aggressive latches (alphas can produce this at 30nm range)
- SOI is 4 to 8 X improvement over bulk (some projections are more pessimistic 2 – 3X, see Sept 2005TDMR)
- We observe the trend to control alpha emissions so alpha contribution is low compared to cosmic
- Some companies set the bar at 0.0002 alphas/cm2/hr
- Is important to consider protecting all SRAM arrays and register files
- At the system level, we heard the lesson to “set your targets”: not just uncorrectable errors but SDC\

- We saw how 3 companies are doing accelerated measurements at system level
- Measurement of logic derating is still elusive
- Low cost (power & area & performance) is essential: 10% chip area increase is a reasonable target for many applications
- Corollary: It is not practical to protect everything (for most applications)
- We saw good progress on methods to tell us how to design for low cost mitigation
- Will we have tools in the future?
- Mitigation techniques should address other failure modes (hard, intermittent, etc.) too
- We saw some ways for programs to be SER-resilient
- We should revisit reliability metrics (beyond MTTF)