SELSE Workshop

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Silicon Today, Silicon Tomorrow

In spite of numerous predictions to the contrary, Silicon technology is marching along past the 22nm node and on to ever finer dimensions. Innovations at the technology, device, circuit and system levels continue to enable us to scale in spite of what sometime appear to be insurmountable problems in power, lack of performance, manufacturability and so on. To a large degree, these innovations are necessary because no substitute technology has been found as yet and, in fact, it does not appear likely that any such technology will become practical this decade. This leaves us with the need to anticipate and predict the near and medium term futures of CMOS for the next handful of technology nodes. Two major challenges for scaling are Lithography (the ability to create small silicon structures) and Power (the efficiency with which we can computation per unit of energy). Another challenge, Resilience, is somewhat less popular, and demands that circuits continue to operate in spite of challenges like noise, difficult environmental conditions, aging and manufacturing imperfections. These factors conspire to cause transient or permanent errors that are indistinguishable from traditional "hard" faults typically caused by defects during fabrication. Without significant innovation at the circuit and system levels, the probability of these events can rise quite dramatically. In the area of SRAM, such phenomena have existed for many technology nodes, but significant investments in this area have indeed allowed continued system level scaling with ever larger on-chip memories. As these same phenomena start attacking integrated circuits more pervasively, there is an urgent need for research and development in this area to avert the problems certain to arise with increased defect rates.

Sani R. Nassif

Sani received his Bachelors degree with Honors from the American University of Beirut in 1980, and his Masters and PhD degrees from Carnegie-Mellon University in 1981 and 1985 respectively. He then worked for ten years at Bell Laboratories in the general area of technology CAD, focusing on various aspects of design and technology coupling including device modeling, parameter extraction, worst case analysis, design optimization and circuit simulation. While at Bell Labs, working under Larry Nagel -the original author of Spice, he led a large team in the development of an in-house circuit simulator, named Celerity, which became the main circuit simulation tool at Bell Labs.
In January 1996, he joined the then newly formed IBM Austin Research Laboratory (ARL), which was founded with a specific focus on research for the support of IBM's Power computer systems. After ten years of management, he stepped down to focus on technical work again, and he is currently working on applying techniques developed in the VLSI-EDA area to IBM's Smarter Planet initiative.
Sani has authored numerous conference and journal publications, and delivered many tutorials at top conferences. He has received Best Paper awards from TCAD, ICCAD, DAC, ISQED, ICCD and SEMICON, authored invited papers to ISSCC, IEDM, IRPS, ISLPED, HOTCHIPS, and CICC. He has given Keynote and Plenary presentations at Sasimi, ESSCIRC, BMAS, SISPAD, SEMICON, VLSI-SOC, PATMOS, NMI, ASAP, GLVLSI, TAU, and ISVLSI. He is an IEEE Fellow, a member of the IBM Academy of Technology, a member of the ACM and the AAAS, and an IBM master inventor with more than 50 patents.
Dr. Nassif is the president elect of the IEEE Council on EDA (CEDA), and was the General chair of the ICCAD conference in 2008. He has previously also served on the technical program committee of ICCAD, DAC and ISQED, and on the executive committee of ISPD. He has received the Penrose award (given to one outstanding graduate from the American University of Beirut), the Distinguished Member of Technical Staff award from Bell Labs, two Research Accomplishment Awards from IBM, and the SRC Mahboob-Khan Outstanding Mentor awards from the SRC.
Sani represents IBM on the SRC Science Area Coordinating Committee for CAD and Test, and is the chair for the committee in 2012. He maintains strong ties with academia, and has participated in PhD committees for students from MIT, CMU, Univ. Minnesota, Univ. Texas Austin, UCSB, UCI, Univ. Glasgow, and Univ. Michigan.