SELSE Workshop

  • Increase font size
  • Default font size
  • Decrease font size
Home

Energy-Efficient Resilience: Challenges and Pitfalls

Presentation Slides: Slides
Abstract:

The cost of maintaining current levels of hardware reliability appears to be unaffordable in the post-22nm late CMOS design era. In the first part of this talk, we will examine the reasons behind such a projection, based on the modeled trends in technology, circuits and microarchitecture. We will show that the energy cost required to sustain targeted levels of system resilience is a central issue. On the other hand, the development cost needed to achieve the target level of energy efficiency, without violating the system resilience constraints is too high, if we approach the problem using current solution approaches.

In the second part of the talk, we will present a vision of cross-layer resilience optimization, which forms the basis of an IBM-led project sponsored by DARPA under its PERFECT program. The goal is to demonstrate through parameterized, cross-layer modeling that such an approach can help provide cost- and energy-efficient resilience in a class of future embedded systems of interest to DARPA, U.S. Department of Defense and also to the general IT appliance industry. The modeling framework is targeted to be flexible enough that customized trade-off analyses are expected to be of value to other R&D efforts geared toward high-end server, mainframe, cloud and large-scale supercomputing market segments as well.

pradibbose

Bio:

PRADIP BOSE is a Distinguished Research StaffMember and Manager of the Reliability- andPower-Aware Microarchitectures Department atIBM T. J. Watson Research Center, YorktownHeights, NY. He has been involved in the designand pre-silicon modeling of virtually all IBMPOWER-series microprocessors, since thepioneering POWER1 (RS/6000) machine, whichstarted as the Cheetah (and subsequentlyAmerica) superscalar RISC project at IBMResearch. From 1992-95, he was on assignment at IBM Austin, where he was the lead performance engineer in a high-end processor development project (POWER3). During 1989-90, Dr. Bose was on a sabbatical assignment as a Visiting Associate Professor at Indian Statistical Institute, India, where he worked on practical applications of knowledge-based systems. His current research interests are in high performance computers, power- and reliability-aware microprocessor architectures, pre-silicon modeling and validation. He is the author or co-author of over ninety refereed publications (including several book chapters) and he also serves as an Adjunct Professor ar Columbia University. He has received twenty Invention Plateau Awards, several Research Accomplishment and Outstanding Innovation Awards from IBM. Dr. Bose served as the Editor-in-Chief of IEEE Micro from 2003-2006 and is the current chairperson of ACM SIGMICRO. He is an IEEE Fellow and a member of the IBM Academy of Technology.