SELSE Workshop

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Panel: Tackling Reliability in Accelerator-Based Systems

Panelists biographies:

Cameron McNairy
is a micro-processor architect for Intel specializing in reliability, availability and serviceability (RAS) for the high performance computing (HPC) segments.  Prior to his work in HPC, Cameron was an architect for the Intel Itanium line of processors focusing on RAS and firmware.  Cameron has been awarded 8 patents, authored or co-authored 7 papers, and has spoken in many forums on a wide variety of topics relevant to the HPC and mission critical computing challenges. He received a BSEE and a MSEE from Brigham Young University and is a member of the IEEE.

Stephen W. Keckler
is the Senior Director of Architecture Research at NVIDIA and Adjunct Professor of Computer Science at the University of Texas at Austin, where he served as a full-time faculty member from 1998 to 2012. His research team at UT-Austin developed scalable parallel processor and memory system architectures, including non-uniform cache architectures; explicit data graph execution processors; and micro-interconnection networks to implement distributed processor protocols. At NVIDIA, Dr. Keckler focuses on parallel, energy-efficient architectures that span mobile through supercomputing platforms. He is a Fellow of the ACM, a Fellow of the IEEE, an Alfred P. Sloan Research Fellow, and a recipient of the NSF CAREER award, the ACM Grace Murray Hopper award, the President's Associates Teaching Excellence Award at UT-Austin, and the Edith and Peter O’Donnell award for Engineering. He earned a B.S. in Electrical Engineering from Stanford University and an M.S. and a Ph.D. in Computer Science from the Massachusetts Institute of Technology.


Michael Schulte is a Senior Fellow with AMD Research in Austin, Texas, where he leads research and advanced development activities in the areas of power-efficient processor design, heterogeneous computing, and high-performance computing. He currently is the principal investigator on AMD’s FastForward 2 Node Architecture Extreme-Scale Computing Research and Development efforts. Michael is also an Adjunct Faculty Member in the Electrical and Computer Engineering Department at the University of Wisconsin-Madison, where he previously directed the Madison Embedded Systems and Architectures Laboratory. 


Michael Flynn is well known for early work on parallel processing. He directed the Architecture and Arithmetic group at Stanford University for more than 20 years where he is now Emeritus Professor of Electrical Engineering. He is also Chairman of Maxeler Technologies, a UK and US based company dedicated to maximum performance computing.


Austin Lesea received his Bachelor of Science in Electrical Engineering and Computer Sciences, University of California at Berkeley in 1975.  In 1976 he received his Masters of Science in Electrical Engineering and Computer Sciences, University of California at Berkeley in optimization, control, and communications theory

He has spent the first year of his career teaching, and writing the book, Microprocessor Interfacing Techniques (1976, Sybex Publishing, Berkeley, California).  He spent the next 13 years designing telecommunications transmission (copper, fiber optic, digital microwave), switching (PBX and ACD systems), and synchronization systems (building integrated timing systems).  During that time, he spent eight years on the ATIS/ANSI T1 Committees helping write the SONET and TI CPE standards.

Mr. Lesea then spent 11 years at Xilinx where as a Principal Engineer in the IC design group where he has been part of the design efforts for five product families.  His last project was as the lead hardware architect and radiative effects designer for the Xilinx Q5 “rad-hard” by design FPGA device, now in use in orbital space applications (in orbit today, and chosen for many missions).  He then joined Xilinx Research Labs where he been looking at soft error effects for the last few years.

Recent interests also include encryption and security.  At the time of this article, he holds 77 patents.