A PDF copy of the call for paper is available here. Links to the most papers and some presentations are provided below. SELSE is an informal workshop. To encourage widespread participation authors are given the option to not have their papers or presentations published on this web site. We thank all authors for their participation.
Day 1 - March 23rd, 2010 - Stanford University
8:00-8:45 Continental Breakfast and Registration
8:45-9:00 Welcome and Introduction from General Co-Chair and Committee
9:00-10:15 Session I: High Performance Computing
Chair: Charles Recchia (Intel)
Invited Talk : Error Implications for High Performance Computing
John Daly (Center for Exceptional Computing).
10:30-12:15 Session II: Microprocessors I
Chair: Rakesh Kumar (University of Illinois)
Invited Talk : Musings on Intrinsic Errors in Modern Microprocessors.
Janak Patel (University of Illinois).
Formal Diagnosis of Hardware Transient Errors in Programs
13:15-15:00 Session III: SER Measurement 1
Chair: Allan Silburt (Cisco Systems)
Invited Talk : Measurement Techniques
Steve Wender, (Los Alamos National Laboratories).
Accuracy of Various Broad Spectrum Neutron Sources for Accelerated Soft Error Testing
The Impact of New Technology on Soft Error Rates
15:15-16:45 Session IV: SER Measurement 2
Chair: Vinod Ambrose (Intel)
Neutron Soft Error Rate Testing of AMD Microprocessors
Measurement Results of Multiple Cell Upsets on a 65nm Tapless Flip-Flop Array.
A Multi-Partner Soft Error Rate Analysis of an InfiniBand Host Channel Adapter.
17:00-18:00 Panel: Relating Measured Soft Error Measurements to Predicted Behaviours
18:00 Reception and Dinner
Day 2 - March 24th, 2010 - Stanford University
8:00-8:45 Continental Breakfast
8:45-10:30 Session V: Circuit Level Modeling and Measurement
Chair: Steve Walstra (Intel)
Invited Talk : Modeling and Analysis of SER In Combinational Circuits
Natasa Miskov-Zivanov, Unversity of Pittsburgh.
On the Radiation-Induced Soft Error Performance of Hardened Sequential Elements in Advanced Bulk CMOS Technologies.
10:45-11:45 Session VI: Microprocessors II
Chair: Ishwar Parulkar (Cisco Systems)
Logic Soft Errors in a Parallel CISC Decoder
Using PVF Traces to Accelerate AVF Modeling
Vilas Sridharan and David Kaeli
12:45-14:00 Poster Session
Resil: A Resiliency Hardware/Software Framework for ASIPs.
Concurrent Autonomous Self-Test for Uncore Components in SoCs.
Reliability-Aware Synthesis: XOR Logic Function Case Study.
The Effect of Pipeline Depth on Logic Soft Errors.
A Single Event Transient Tolerant Monolithic Phase-Locked Loop Design.
14:00-15:00 Session VII: Mitigation Techniques
Chair: Adrian Evans (Cisco Systems)
A Novel Bulk Built-In Current Sensor for Single-Event Transient Detection
Tao Wang, Zhichao Zhang, Li Chen, Anh Dinh, and Robert Shuler.
A Numerical Optimization-based Methodology for Application Robustification.
15:15-16:00 Session VIII: Cross Layer Reliability
Chair: Subhashish Mitra (Stanford University)
Invited Talk : Cross-Layer Reliability.
Nick Carter (Intel).
16:00-16:30 Discussion: Cross-Layer Reliability.
16:30-17:00 Closing Remarks